This invention relates to a semiconductor memory device, and more particularly to a function for decoding an address of a high integrated, high speed DRAM, and is suitable for a RAM section of a dual port memory and for picture images in particular.
A dual port memory includes a randomly accessible RAM section and a serially accessible serial access memory section (hereinafter referred to as SAM section). Such a dual port memory is very useful for picture image processing of a CAD, a work station (WS) and so forth, and as improvement in speed and function of a picture image system proceeds, requests for more sophisticated functions and reductions in the access time are progressively increasing.
One of most basic ways of using a dual port memory is real time reading/transferring. In such real time reading/transferring, for example, the SAM side serially outputs the contents of a register while the RAM side writes a series of data in a page mode into a certain row, and the data of the row are transferred at a time from the RAM section to the SAM section, and then the SAM side continuously outputs the transferred data from an address received upon such transfer.
In this instance, only those data which are outputted for the first time after such transfer follow, due to a restriction in time, a different data path from that of data which are outputted for the second time et seq. Data for the second time et seq. are stored from a certain row of the RAM once into a register at the same column address and are then serially accessed and outputted by a toggle of serial clocks (SC) by which the SAM is controlled. However, only for the first time, not such data that have been transferred to such a SAM register but data stored in a separately provided 1-bit temporary register are transferred directly to an output buffer so that they may be outputted from the dual port memory.
Therefore, on the RAM side, data of a column address received upon transfer must be read out from a cell and stored into a 1-bit temporary register. The foregoing is disclosed in Nikkei Electronics, Aug. 12, 1985, Nikkei McGraw Hill.
Operation of such a dual port memory when 1-bit data are stored into the temporary register will be described first with reference to FIG. 7 in which construction of a column address decoding system and an I/0 line system is shown. Here, however, in order to facilitate description, the number of column addresses to be selected at a time by way of a single column selecting line is determined to be 2 and the column address ranges from 0 to 255. Further, while each of a bit line, a data output line I/0 and so forth is normally in the form of complementary lines and is composed of a set of two lines, it is represented by a single line in FIG. 7. Meanwhile, since a row address is at will, only a selected word line WL.sub.m and a group of memory cells connected to the word line WL.sub.m are shown in FIG. 7.
A column address signal is received from the outside, amplified by a column address buffer 70 and transferred into signal lines 700. If the column address is, for example, 3, then a column decoder CDl which is to be selected when the column address is 2 or 3 will be selected. Thus, a column selecting line CSLl of the column decoder CDl is selected automatically, and consequently, a pair of column gate transistors G2 and G3 are rendered conducting so that data of 2 bits of a memory cell MC2 and another memory cell MC3 are read out into data input/output lines I/00 and I/01, respectively. Then, the 2-bit data thus read out are then decoded and amplified by an I/0 line selecting buffer 10, and in this instance, data of the data input/output line I/01, in short, data from the column address 3, are outputted into a data line 400.
In an ordinary reading operation, a gate 60 is open, and consequently, the data on the data line 400 are once transferred to an output buffer 50 by way of an n address data line pair 410 and then outputted to the outside. When the dual port memory is in a reading/transferring mode, the gate 60 is closed while another gate 65 is open, and consequently, the data on the data line 400 are transferred to and stored into a temporary register 90 by way of another n address data line pair 420. Such operation is not limited to the case wherein the column address is 3, but is similar to another case wherein the column address assumes any other value.
Also, as requests for improvement in speed in accessing to a serial output of the SAM increase, new techniques for high speed operation have been proposed. One of such techniques is a data reading technique called "SAM of the pipeline interleave system". According to such a system, accessing is commenced two cycles prior to an SC cycle in which data are to be outputted. Operation in a case wherein the pipeline interleave system is applied to such real time reading/transferring as described above will be described below with reference to FIG. 8 which shows operation waveforms of several control signals. A row address signal is read in at a falling edge of a row address strobe (RAS) signal, and then a column address signal is read in at a falling edge of a column address strobe (CAS) signal. Here, of a column address signal, a serial access starting address (hereinafter referred to as TAP address) of the SAM is determined to be n. Furthermore, transfer of data is performed at the time of a rising edge of a data transfer/output enable (DT/e,ovs/OE/ ) signal. A serial clock (SC) signal defines a cycle when serial accessing is to be performed. Meanwhile, an address data signal and a serial I/0 signal indicate that accessing is started two SC cycles prior to an SC cycle in which serial outputting of data are to be started. In a first SC cycle immediately after the start of such transfer, data corresponding to a column address signal n must be outputted while data corresponding to another column address signal n+2 are accessed from the SAM register, but in a second SC cycle, data corresponding to a column address signal n+1 must be outputted while data corresponding to another column address signal n+3 are accessed from the SAM register.
In short, data of 2 bits corresponding to the column address signals n and n+1 must be sent out not from the SAM register but directly from the RAM side to the output buffer of the SAM side. Accordingly, the RAM side is required to have a function of reading out such two bits at a time and a 2-bit temporary register for storing such two bits therein.
Here, with the conventional arrangement shown in FIG. 7, data, for example, at the column addresses 2 and 3, can be read out at a time into the data output lines I/00 and I/01 and finally stored into the temporary register 90 in the form of a 2-bit register. However, the column addresses 3 and 4 cannot be selected at the same time, since they correspond to the two column selecting lines CSLl and CSL2, respectively. In short, with the conventional arrangement shown in FIG. 7, data at the column addresses n and n+1 cannot be read out at the same time.
Several improved techniques have been proposed in order to remove such a drawback. Exemplary ones of such improved techniques will be described subsequently. First, an improved conventional arrangement will be described with reference to FIG. 9. It is to be noted that like elements to those of FIG. 7 are denoted by like reference characters in FIG. 9.
When data at certain column addresses n and n+1 are to be read out, a column decoder CD.sub.n is selected in accordance with a column address n. In the case where such column address n is 255, column decoders CD255 and CD-1 are selected. When the column address n is an even number, for example, when n=2, a column decoder CD2 is selected, and then the level at a signal line SL0 is put into a high potential by an LBS selecting circuit 20. Consequently, two column gate transistors G2 and G3 are opened. As a result, data of memory cells MC2 and MC3 are read out into data output lines I/00 and I/01, respectively. On the other hand, in case the column address n is an odd number, for example, when n=1, a column decoder CDl is selected level at a signal line SLl is put to a high potential, two column gate transistors Gl and G2 are opened. As a result, data of memory cells MCl and MC2 are read out into data output lines I/01 and I/00, respectively. As a column decoder CD.sub.n and the signal line SL0 (when the column address n is an even number) or the signal line SLl (when the column address n is an odd number) are selected in this manner, data at the desired column addresses n and n+1 can be read out at a time into an I/0 line selecting buffer 10.
Furthermore, when data of 2 bits are to be transferred to a temporary register 90 while the dual port memory is in a reading/transferring mode, decoding is not performed at the I/0 line selecting buffer 10, and when the column address n is an even number, the data output lines I/00 and I/01 are connected to data lines 400 and 450, respectively, but when the column address n is an odd number, the data output lines I/00 and I/01 are connected to the data lines 450 and 400, respectively. Then, since a gate 60 is closed while another gate 65 is open, data at the column addresses n and n+1 are finally transferred to and stored into the temporary register 90 at a time.
On the other hand, in an ordinary reading mode, it is only necessary that data at a column address n can be transferred to an output buffer 50. Accordingly, decoding is performed for a least significant bit (LSB) of a column address signal by the I/0 line selecting buffer 10, and finally decoded data are transferred to the data line 400. Since the gate 60 is open while the gate 65 is closed, only data at the column address n are sent to the output buffer 50 and outputted to the outside.
Also such an arrangement as shown in FIG. 10 has been proposed. Referring to FIG. 10, the arrangement shown includes a control section 100 which is similar to that of the arrangement shown in FIG. 9. When a column address n is received, a column address decoder CDn is selected so that the level at a column selecting line CSL.sub.n is changed to a high potential. The column selecting line CSL.sub.n places a pair of column gate transistors GA.sub.n and GB.sub.n connected thereto into a conducting condition so that data of memory cells MC.sub.n and MC.sub.n+1 are read out into data output lines I/00 and I/01, respectively (when n is an even number) or into the data output lines I/01 and I/00, respectively (when n is an odd number). Operation of the arrangement after then, is similar to that described hereinabove in connection with the arrangement shown in FIG. 9.
In this manner, the improved conventional arrangements shown in FIGS. 9 and 10 are characterized in that bit lines BL.sub.n and BL.sub.n+1 connected to memory cells MC.sub.n and MC.sub.n+1, respectively, for each column address n are directly connected to the data output lines 1/00 and I/01 or I/01 and I/00, respectively, and two column decoders CD.sub.n and CD.sub.n-1 can be connected to a single bit line BL.sub.n. Accordingly, with the arrangements, it is possible in principle to have a construction such that an arbitrary number of bits not only from two column
The two improved arrangements, however, have the following problems.
First, when the number of column addresses is N, a number of column decoders equal to 2.sup.N is required, which is not advantageous to high integration. Further, as a second problem, it is impossible in principle to replace part of the arrangement with a spare element or elements.
The first problem will be described in more detail first. In the two improved arrangements, all bit lines must be decoded completely with the column decoders. Accordingly, a number of column decoders equal to the number of column addresses are required, which makes an obstacle to high integration. In most cases, particularly the RAM section of a dual port memory is required to be constituted so as to be able to effect block writing wherein same data are written at a time into columns of 2.sup.i (i is an integer equal to or greater than 1) bits. To this end, a construction is employed in most cases such that a column of 21 bits is selected by way of a single column selecting line CSL to read out data into a 2.sup.i pairs of data output I/00 lines, and 1/2.sup.i decoding is effected by the I/0 line selecting buffer 10. However, since the number of column addresses n which belong to such a single column selecting line CSL is only two, block writing is generally impossible with any of the improved arrangements described above.
Subsequently as the second problem, since 2 bits are necessarily selected by way of a single column selecting line CSL, in case, for example, the column addresses 4 to 7 are replaced by a spare cells, when the column address is 3, it is necessary to access data at the memory cell MC3 of the normal column and at a memory cell of the first column of the spare memory cells, but such accessing is impossible with any of the conventional arrangements.
As described so far, the arrangement shown in FIG. 7 cannot cope with a pipeline interleave system, and the arrangements shown in FIGS. 9 and 10 which are improved in that point have critical problems as a RAM section for a dual port memory that high integration cannot be achieved readily and replacement of a faulty cell with a spare cell is impossible.